This invention pertains to computer systems and other information handling systems and, more particularly, to a computer system employing a multiplexed address/data bus in which xe2x80x9cturnaround cyclesxe2x80x9d or xe2x80x9cwait cyclesxe2x80x9d are eliminated.
In the design of computer buses, the reduction in the total number of signal lines is frequently an important criterion. From a mechanical design standpoint, reducing the total number of lines also reduces the total number of pins for any connector that is coupled to the bus. One way to reduce the total number of lines is to xe2x80x9ctime multiplexxe2x80x9d the address and data signals such that there is only one set of xe2x80x9caddress/dataxe2x80x9d lines that carry both address and data information, but at different times. In other words, during certain intervals of time address information is transmitted over the address/data lines, while data is transmitted over these same lines during other intervals of time.
One such industry standard bus is the Peripheral Component Interconnect bus or PCI bus. On the PCI bus, 32 bits of address information and 32 bits of data are transmitted over the same 32 address/data lines. If the PCI bus did not use time multiplexing, a total of 64 lines would be needed just to carry the address and data information. Consequently, for PCI, the use of time multiplexing for the address and data signals reduces the total number of signal lines by 32, which also reduces the bus connector xe2x80x9cpin countxe2x80x9d by the same amount. Consequently, when compared to other competing buses that do not multiplex the address and data signals, the PCI bus has about half the total number of signal lines.
Since two or more devices can drive the bus, electrical contention problems can result. These contention problems are caused by the first device""s failure to relinquish the bus before the second device takes over. Consequently, for a brief interval of time, two bus driver circuits coupled to the same line on the bus may be simultaneously attempting to drive that line to two different logic levels. These contention problems become more acute with increased bus speeds.
To alleviate this electrical contention problem, it is common in the industry to have xe2x80x9cturnaround cyclesxe2x80x9d or xe2x80x9cwait cyclesxe2x80x9d allocated between the time when one device is driving the bus and the time when another device takes over. The disadvantage to the insertion of turnaround cycles, however, is that they decrease data throughput. For example, on the PCI bus, turnaround cycles reduce the data throughput by 50% for all non-burst mode read cycles, and for non-burst mode write cycles involving either a change of initiator or target device the throughput is reduced by 33%.
The term xe2x80x9cback-to-back writexe2x80x9d or xe2x80x9cback-to-back readxe2x80x9d refers to two or more consecutive data transfer operations (i.e., read or write operations) in non-burst mode between the same initiator device and the same target device, with or without turnaround cycles. For non-burst mode data transfers, address information is transmitted over the bus at the beginning of each individual data transfer operation. For burst mode data transfers, however, consecutive data transfer operations are read from or written to consecutive address locations so that the base address information is only transmitted once at the beginning of each burst of data. The term xe2x80x9cconventional back-to-back transferxe2x80x9d refers to a back-to-back transfer that includes turnaround cycles, while the term xe2x80x9cfast back-to-back transferxe2x80x9d refers to a back-to-back transfer in which turnaround cycles have been eliminated.
One method for the elimination of turnaround cycles for back-to-back write operations is described in U.S. Pat. No. 5,448, 703. According to this patent, a PCI initiator uses address range checking hardware to detect that two consecutive write cycles are to the same physical target device, and then eliminates turnaround cycles for this type of write operation. This technique for eliminating turnaround cycles for back-to-back writes has been incorporated into version 2.0 of the PCI specification. The""703 patent, however, also explicitly excludes read cycles as candidates for fast back-to-back transfers.
The industry solution to the turnaround cycle problem has another drawback; specifically, write throughput is different from read throughput. Since certain software applications require symmetrical read and write rates, it is necessary to slow the write rate down to equal that of the slower read rate. However, the calculation of the different read and write rates in software is not a trivial problem. Thus, it is desirable for the read throughput and the write throughput to be the same.
Contention is particularly problematic on a multiplexed address/data bus when an initiator device performs a read operation on a register in a target device. Since the initiator device places the address information on the address/data lines first, followed by the target device driving the register data onto the same address/data lines, a turnaround or wait cycle is inserted between the address cycle and the data cycle to prevent contention between the driver circuits in the initiator and the driver circuits in the target. Furthermore, for conventional back-to-back read operations, a turnaround cycle must also be inserted after the target device places data on the address/data lines to separate the previous data cycle from the next address cycle.
Accordingly, the invention described below eliminates turnaround cycles not only for back-to-back writes, but also for back-to-back reads. The elimination of turnaround cycles not only doubles the data throughput for back-to-back read operations, but also makes the data throughput for fast back-to-back read operations equal to the data throughput for fast back-to-back write operations.
To accomplish these advantages, the current invention utilizes a three mode (5state) bus driver circuit, which is described in a related patent application Ser. No. 09/162,618 (now U.S. Pat. No. 6,088,756) and which was filed on the same date as this application. This co-pending application, which is incorporated into this application by reference, is entitled xe2x80x9cFive State Bus Driver Having Both Voltage And Current Source Modes Of Operationxe2x80x9d.
Briefly, the invention is a method and apparatus for performing data read operations between an initiator device and a target device that are coupled to a bus. A clock signal on one line of the bus includes a plurality of clock cycles wherein each clock cycle includes a first and a second phase. Each of the initiator and target devices includes a three mode bus driver having three selectable modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is a Hi-Z mode having high output impedance. During a first clock cycle, the third mode of operation is selected for the driver of the target device. The initiator device drives a first address onto the bus during the first clock cycle. For the driver of the initiator device, the first mode of operation is selected during the first phase of the first clock cycle and the second mode of operation is selected during the second phase of the first clock cycle. During a second clock cycle, the third mode of operation is selected for the driver of the initiator device, and the target device drives first data onto the bus. For the driver of the target device, the first mode of operation is selected during the first phase of the second clock cycle, and the second mode of operation is selected during the second phase of the second clock cycle.
In another embodiment, the invention is a method and apparatus for performing a data write operation from an initiator device to a first target device that are coupled to a bus. A clock signal on one line of the bus includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase. Each of the initiator and target devices includes a three mode bus driver having three selectable modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is Hi-Z mode having very high output impedance. During a first and a second clock cycle, the third mode of operation is selected for the driver of the first target device. The initiator device drives a first address onto the bus during the first clock cycle. For the driver of the initiator device, the first mode of operation is selected during the first phase of the first clock cycle. During the second clock cycle, the initiator device drives first data onto the bus. For the driver of the initiator device, the first mode of operation is selected during the first phase of the second clock cycle, and the second mode of operation is selected during the second phase of the second clock cycle.
In still another embodiment, the invention is a method and apparatus for performing a data write operation from an initiator device to a first target device. A clock signal on one line of the bus includes a plurality of clock cycles, wherein each clock cycle includes a first and a second phase. A control signal on a control line of the bus has active and inactive states, wherein the active state is asserted when the target device is ready to accept data from the initiator device. The first target device includes a three mode bus driver having three selectable output modes of operation. The first mode of operation is a voltage mode having a voltage output corresponding to the logical state of the data input to the driver and having a low output impedance. The second mode is a current mode having a voltage output corresponding to the logical state of the data input to the driver and having a high output impedance. And the third mode is Hi-Z mode having very high output impedance. The three mode bus driver of the first target device is coupled to the control line of the bus. The initiator device places a first address on the bus during a first clock cycle. The target device drives the control line active during the second clock cycle. During the first phase of the second clock cycle, the first mode of operation is selected for the driver of the first target device, while the second mode of operation is selected during the second phase of the second clock cycle. During the second clock cycle, the initiator device places first data on the bus.